EDA技术基础实验报告实验项目名称：__________________7段显示译码器设计学院专业：______________________信息学院电子专业姓名：__________________________________________________学号：__________________________________________________实验日期：______________2实验成绩：_______________________实验评定标准：1）实验结果是否合理A()B()C()2）实验分析是否正确A()B()C()3）实验报告是否按照规定格式A()B()C()实验目的学习7段显示译码器设计，学习VHDL的CASE语句应用及多层次设计方法。二、实验器材QuartusII软件三、实验原理及内容计数器和译码器连接电路顶层设计图（1）1.图（1）中，计数器叫CNT4B,显示译码器叫DECL7S,在下面程序中CNT4B的名字改作four_addero四、实验程序1.顶层文件的程序设计:LIBRARYIEEE;USEIEEE.STD_L0GIC_1164.ALL;ENTITYmainISPORT(CLOCKO:INSTD.LOGIC;-时钟输入ENA0:INSTD_LOGIC;-使能端，为高电平时，显示器保持零RST0:INSTD_LOGIC;--复位端，高电平时，显示清零，返回低电平后，重新从零开始递增显示COUTO:OUTSTD_LOGIC;-循环显示一周，给出一个通知信号led:OUTSTD丄OGIC_VECTOR(6DOWNTO0);--将数字信号送入显示管ledOs:OUTSTD_LOGIC_VECTOR(3DOWNTO0));-显示数码管的数字，便于波形观察ENDmain;2.建立顶层文件波形并仿真，截下仿真结果图。ARCHITECTUREarcOFmainIS--第一个元件(显示译码器)例化声明COMPONENTDECL7SPORT(A:INSTD_LOGIC_VECTOR(3DOWNTO0);LED7S:0UTSTD_L0GIC_VECT0R(6DOWNTO0);-将数字信号送入led显示管LEDSO:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ledOs--显示数码管的数字,信号送入ENDCOMPONENT;COMPONENTfour_adderPORT(CLK:INSTD.LOGIC;ENA:INSTD_LOGIC;RST:INSTD.LOGIC;COUT:OUTSTD_LOGIC;-第二个元件（四位二进制计数器）例化声明-内部元件时钟输入-内部元件使能端--内部元件复位端-循环显示一周，给出一个通知信号OUTY:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCOMPONENT;SIGNALtemp:STD_LOGIC_VECTOR(3DOWNTO0);BEGINU1:four_adderPORTMAP(CLK=>CLOCKO,ENA=>ENAO,RST=>RSTO,OUTY=>temp,COUT=>COUTO);V1:DECL7SPORTMAP(A=>temp,LEDS0=>led0s丄ED7S=>led);ENDarc;2.计数器的程序设计：LIBRARYIEEE;USEIEEE.STDLOGIC1164.ALL;USEIEEE.STD_LOGIC_SIGNED.ALL;ENTITYfour_adderISPORT(CLK:INSTD.LOGIC;ENA:INSTD.LOGIC;RST:INSTD.LOGIC;COUT:OUTSTD.LOGIC;"时钟输入--使能端--复位端-循环显示一周，给出一个通知信号OUTY:OUTSTD丄OGIC_VECTOR(3DOWNTO0));ENDfour_adder;ARCHITECTUREadderOFfour_adderISSIGNALS:STD丄OGIC_VECTOR(3downto0);BEGINPROCESS(CLK,ENA,RST,S)BEGINIFENATHENIFRST=,O,THENIFCLK'EVENTANDCLK"THENIFS=n11HMTHENC0UT<=*1:S<=H0000H;ELSES<=S+,1,;COUT<=,0,;ENDIF;ENDIF;ELSES<=H0000n;ENDIF;ENDIF;ENDPROCESS;OUTY<=S;ENDadder;3.显示译码器的程序设计：LIBRARYIEEE;USEIEEE.STDLOGIC1164.ALL;ENTITYDECL7SISPORT(A:INSTD_LOGIC_VECTOR(3DOWNTO0);LEDSO:OUTSTD_LOGIC_VECTOR(3DOWNTO0);-显示数码管的数字，便于波形观察LED7S:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDDECL7S;ARCHITECTUREoneOFDECL7SISBEGINPROCESS(A)BEGINCASEAISWHEN”0000”二〉LED7S<=H01:LEDSO<=n0000n;WHEN”000V=>LED7S<=H0000110H;LEDSO<=n0001n;WHEN”0040”=>LED7S<=H1011011H:LEDSO<=n0010”;WHENn00HH=>LED7S<=H1001111M:LEDSO<=n0011n;WHEN”0100”=>LED7S<=H1100110":LEDSO<=n0100n;WHEN,,010T,=>LED7S<=H1101101H:LEDSO<=n0101n;WHENH0110H=>LED7S<=H1111101":LEDSO<=n0110n;WHENH0111H=>LED7S<=H0000111”:LEDSO<=n0111n;WHEN”1000”=>LED7S<=H1111111";LEDSO<=n1000”;WHEN"lOOT*=>LED7S<=H1101111H:LEDSO<=n1001n;WHENH1010H=>LED7S<=H1110111M:LEDSO<=n1010n;WHEN"101T*=>LED7S<=H1111100H:LEDSO<=n1011n;WHENH1100H=>LED7S<=H0111001“:LEDSO<=n1100”;WHEN,,110T,=>LED7S<=H1011110H:LEDSO<=n1101n;WHENH1110H=>LED7S<=H1111001“:LEDSO<=n1110n;WHENH1111H=>LED7S<=H1110001H:LEDSO<=n1111n;ENDCASE;ENDPROCESS;ENDone;五、实验仿真结果及分析1.顶层设计的波形仿真图如下：顶层设计的波形仿真图（2）分析:在时钟脉冲CLOCKO的作用下，ENAO使能端权限最高，当其为高电平时，数码管led显示保持“0”；当ENA0为低电平时，权限较低的是RST0复位端，实现数码管清零，回归为低电平后，数码管显示数字从“0”递增到“F”，ledOs在波形图中的作用是便于观察数码管的显示数字字符。CLDCKDEMALRSKCOUTOled-led[5]-led[4]-l